One of the goals of very large scale integration is to increase the amount of memory available on an integrated memory circuit while maintaining or decreasing the overall size of the integrated circuit. Dynamic Random Access Memory (DRAM) capacity has increased from 64K up through the 1 megabyte level and beyond on one chip. As the size of the memory capacity increases, the concentration of memory cells increases. Various techniques have been utilized to squeeze as many memory cells onto a chip as possible.
Three basic types of memory cells are currently used. First, the flat memory cell, as its name implies, uses a flat capacitor (built with its plates parallel to the surface of the substrate) and transistor for each memory cell. The disadvantage of this configuration is that as the surface area available for each capacitor decreases, the capacitance, or the ability to hold the charge representing the memory unit, decreases.
Second, trench capacitors have been used. A trench capacitor utilizes a well formed into the substrate, whereby the electrical charge representing the memory unit is stored on a capacitor between the heavily doped wall of the trench and the electrode in the trench. One major drawback of this type of capacitor is leakage of the charge from the trench wall to adjacent capacitors if the substrate is not heavily doped or the trench cells are too close together.
Third, stacked capacitors have been used. A stacked capacitor is a capacitor which can, because of its construction, overlap or "stack" on top of other elements of the cell (i.e., the word line or isolation layer). The disadvantage of this cell is that as the surface area is reduced the capacitor decreases.
One solution that has been proposed to these various problems is to fabricate two capacitors one on top of the other using flat capacitor fabrication techniques. This structure can utilize the capacitance of the capacitors in parallel (C.sub.total =C.sub.1 +C.sub.2), whereby the total surface area of the capacitor may be made smaller than a one-capacitor memory cell, and have the same or greater capacitance. As a result, integration may take place on a larger scale.
One major problem with multiple capacitors is that it is very difficult to connect the upper capacitor plate to the pass transistor which controls access to the memory cell. This is true, in general, for connecting one level to another in all multi-layer structures. In standard processing, an insulating layer is normally placed on top of the upper capacitor plate. Small holes are etched to both the upper plate and the pass transistor (on the order of one square micron each) and a layer of metal would be deposited to connect the two layers.
Making this type of connection is very space consuming, and the closest the metallic contact layer may approach the edge of the memory cell or pass transistor gate is defined by the alignment tolerances and the etch tolerances of the system used in manufacture. Therefore, a multiple capacitor memory cell has not heretofore been practical.
It is therefore a general object of this invention to overcome the above problems.
A further object of this invention is to provide a memory cell with high capacitance in a small area.
A further object of this invention is to provide a contact region with a minimal amount of addition processing.
Yet a further object of this invention is to provide a method of fabricating a multilayered integrated circuit which provides a contact from an upper layer to a lower layer in the circuit without shorting to any conductive layers in between.